1. Field of the Invention
The present invention relates to a sampling circuit and method for sampling digital data.
2. Description of the Related Art
In an electronic apparatus for electronic exchange and data transfer, a sampling circuit as shown in FIG. 3 is employed for sampling digital data. The sampling circuit it uses a D type flip-flop IC (integrated circuit), one of the existing general-purpose IC, as shown in FIG. 3. As shown in FIG. 3, the sampling circuit is composed of tri-state inverters 11, 12, 21 and 22.
The tri-state inverters 11, 12, 21 and 22 have their own input signals prevented from emerging as their own output signals when their control gates receive logic level "H" signal and have their own input signals appear as output signals when they receive a logic level "L" signal.
A series circuit of inverters 52 and 53 constitutes a timing control circuit. The timing control circuit is of such a type that, when a system drive clock pulse CLK is input to the series circuit of the inverters 52 and 53, level-inverted HIGH and LOW signals, that is, two types of drive signals .phi. inverted signal) and .phi. are obtained in an in-phase relation.
The drive clock signal .phi. serves as a drive clock for driving the tri-state gates 11 and 12 and the drive clock signal .phi. (inverted signal) serves as a drive clock for the tristate gates 21 and 22. For this reason, when the tri-state gates 11 and 12 are in the operative state, the tri-state gates 21 and 22 are in the inoperative state. When the tri-state gates 11 and 12 are in the inoperative state, the tri-state gates 21 and 22 are in the operative state.
Input data DI is supplied via the tri-state gate 21 and forwarded via the inverter 51, tri-state gate 12 and AND gate 31 NOR gate 41. The tri-state gate 11 is connected in reverse-parallel with an inverter 51. With the clock pulse CLK in the logic level "L" , the flip-flop circuit receives the input data DI. The received data DI is held as hold data DT by the reverse parallel circuit of the inverter 51 and tri-state gate 11 and is delivered as an output when the clock pulse CLK becomes a logic level "H".
The output data is delivered as output data DO to an outside circuit via a series circuit of AND circuit 31 and NOR gate 41. The tri-state AND gate 22 is connected in reverse parallel with the series circuit of the AND gate 31 and NOR gate 41. During the "L" period of the clock pulse CLK, the output data of the NOR gate 41 is fed back to the AND gate 31, holding an output of the series circuit of the AND gate 31 and NOR gate 41.
Upon receipt of a preset signal PST (the logic level "H"), the AND gate 31 allows the passage of an input signal which is received at the other terminal thereof and, upon receipt of a preset signal (the logic level "L"), produces an output "L". Upon receipt of the reset signal RST (the logic level "H"), the NOR gate 41 clears the hold data of the reverse parallel circuit of the AND gate 31, NOR gate 41 and tri-state gate 22.
The operation of the aforementioned circuit will be explained below, by way of example, by referring to the timing chart shown in FIG. 4.
Upon receipt of a clock pulse CLK (see FIG. 4B), the timing control circuit generates drive clock signal .phi. and .phi.. The flip-flop circuit of FIG. 3 is operated by applying the drive clock signals .phi. and .phi. to the tristate gates 21, 22 and 11, 12, respectively.
With the preset signal PST (see FIG. 4C) and reset signal RST (see FIG. 4D) in the logic levels "H" and "L", respectively, input data DI (see FIG. 4A) is taken out in the circuit of FIG. 3 via the tri-state gate 21 when the clock pulse CLK is varied to the logic level "L". The input data DI thus taken is held, as held data DT (see FIG. 4E), by the reverse parallel circuit of the inverter 51 and tri-state gate 11.
At this time, the clock pulse CLK is in the logic level "L" and the tri-state gate 22 is placed in the inoperative state and hence the hold data is not delivered as an output.
With the clock pulse CLK in the logic level "H", the tri-state gate 21 is placed in an inoperative state and, instead, the tri-state gate 22 is operated, allowing the hold data DT to be delivered as an output of the gate 22 to the AND gate 31.
The hold data DT is output as sampling output data DO to an output terminal via the AND gate 31 and NOR gate 41. During the logic level "L" of the clock pulse CLK, the sampling output data DO of the output terminal is fed back to the AND gate 31 and supplied via the series circuit of the AND gate 31 and NOR gate 41 to the output terminal. In this way, the output data DO is held.
With the clock pulse in the "L" level, the next input data DI is received by the flip-flop circuit DI and is held as hold data DT by the reverse parallel circuit of the inverter 51 and tri-state gate 11. With the clock pulse CLK in the "H" level, the hold data DT is delivered as an output via the series circuit of the AND gate 31 and NOR gate 41.
The tri-state gate 22 is connected in reverse parallel with the series circuit of the AND gate 31 and NOR gate 41. With the drive clock signal .phi. in the logic state "L", the output data of the NOR gate 41 is fed back to the AND gate 31, holding the output of the series circuit of the AND gate 31 and NOR gate 41. In synchronism with the clock pulse CLK, the input data DI is sampled and output.
Since the sampling circuit utilizes the operation of the D type flip-flop, it holds the input data at the time of a synchronizing clock pulse and operates such that the hold data held by the clock pulse prior to a one-clock time is used as an output of the sampling circuit. For this case, the resolution time corresponds to the pulse width of the clock pulse CLK which is the sampling clock. The sampling clock becomes a sampling frequency. In order to obtain a target resolution, a high sampling frequency is required and hence a sampling clock of a corresponding frequency is necessary.
In the aforementioned conventional sampling circuit, in general, when digital data is to be sampled, it is necessary to use a clock pulse of a sampling frequency corresponding to double the bit rate of data for a synchronous system and a clock pulse of a sampling frequency corresponding to four-times the bit rate of data for an asynchronous system.
In the aforementioned conventional sampling circuit, it is necessary to use a sampling clock of 16 to 32 MHz if the bit rate of the data to be handled is, for example 8 Mbps.
If the sampling clock to be used becomes such a high frequency, it causes an operation error in a peripheral circuit due to a fine noise spike induced. In the peripheral circuit, therefore, proper preparation needs to be made against such a noise which might otherwise cause a serious problem in the peripheral circuit under an electromagnetic circumstance.
In recent times, higher and higher bit rate has been required for the data to be handled and hence a higher processing is necessary in view of such a tendency. If, under such a circumstance, use is made of a sampling clock of a frequency two-to four-times the data transfer rate as in the conventional sampling circuit, the peripheral circuit suffers a more serious electromagnetic problem.
There is growing demand for a sampling circuit which can operate with a sampling clock of a lower frequency and can obtain a higher resolution in the sampling of data.